Module Details
| Module Code: |
COMP9097 |
| Title: |
TinyML Engineering
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Long Title:
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TinyML Engineering
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| NFQ Level: |
Expert |
| Valid From: |
Semester 1 - 2024/25 ( September 2024 ) |
| Field of Study: |
4811 - Computer Science
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| Module Description: |
Tiny Machine Learning (TinyML) involves the deployment of Machine Learning models to microcontrollers and other low-power devices at the edge of a network. TinyML engineering involves the design and deployment of ML models on such devices, which target various applications (e.g., predictive maintenance, activity tracking, health monitoring). The module explores the tools, frameworks, technologies, platforms, and methods used to create TinyML devices. The focus of the module is the engineering of Machine Learning (ML) based software architectures for such systems. The module explores methodologies and technologies for the acceleration of TinyML systems.
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| Learning Outcomes |
| On successful completion of this module the learner will be able to: |
| # |
Learning Outcome Description |
| LO1 |
Appraise embedded software development techniques and methodologies for TinyML platforms. |
| LO2 |
Critique TinyML system design methodologies for the monitoring and control of a physical environment. |
| LO3 |
Design a TinyML device using frameworks and signal processing techniques. |
| LO4 |
Investigate compilation ecosystems and interpretation techniques for the efficient execution of TinyML systems. |
| LO5 |
Develop systems for the hardware acceleration of TinyML devices. |
| Dependencies |
Module Recommendations
This is prior learning (or a practical skill) that is strongly recommended before enrolment in this module. You may enrol in this module if you have not acquired the recommended learning but you will have considerable difficulty in passing (i.e. achieving the learning outcomes of) the module. While the prior learning is expressed as named MTU module(s) it also allows for learning (in another module or modules) which is equivalent to the learning specified in the named module(s).
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Incompatible Modules
These are modules which have learning outcomes that are too similar to the learning outcomes of this module. You may not earn additional credit for the same learning and therefore you may not enrol in this module if you have successfully completed any modules in the incompatible list.
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| No incompatible modules listed |
Co-requisite Modules
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| No Co-requisite modules listed |
Requirements
This is prior learning (or a practical skill) that is mandatory before enrolment in this module is allowed. You may not enrol on this module if you have not acquired the learning specified in this section.
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| No requirements listed |
| Indicative Content |
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Embedded software development for TinyML systems
Embedded Systems; Constrained platforms for TinyML systems e.g. memory and processor constraints on an embedded system; Architectures e.g. ARM, RISC-V; Platforms e.g. STM32F7 Discovery; Jetson Nano; Bare metal runtime environment; Operating Systems; Embedded System Firmware.
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TinyML system monitoring and control
Internet of Things (IoT); Cyber Physical System e.g. drone flight control; STM32Cube firmware; Input/Output peripherals; Analog-to-digital conversion (ADC); Sensors: IMU, audio; Signal Processing; DSP on a resource constrained device.
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TinyML system design
Software frameworks for TinyML systems e.g. TFlite; TFlite tensor processing architecture; Signal processing on a constrained platform. Case studies e.g. anomaly detection - identify machine failures, audio processing, voice control.
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ML model abstractions
Compilation vs interpretation of ML models; Computational graph
model and abstractions; TensorFlow Compiler ecosystem; Case studies: MLIR; TVM; Lowering of abstractions.
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Hardware Acceleration
Architecture of a GPU; Threading; Parallelism; GPU programming; CUDA Parallelism Model; Software Synthesis on FPGAs; Hardware Description Language (HDL): Verilog, Chisel; Case study: Gemmini - the DNN hardware exploration and evaluation platform; CUDA DNN frameworks; Tensor Processing Unit (TPU).
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Module Content & Assessment
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| Assessment Breakdown | % |
|---|
| Coursework | 100.00% |
Assessments
| No End of Module Formal Examination |
| Reassessment Requirement |
Coursework Only
This module is reassessed solely on the basis of re-submitted coursework. There is no repeat written examination.
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The University reserves the right to alter the nature and timings of assessment
Module Workload
| Workload: Full Time |
| Workload Type |
Contact Type |
Workload Description |
Frequency |
Average Weekly Learner Workload |
Hours |
| Lecture |
Contact |
Lecture delivering theory underpinning learning outcomes. |
Every Week |
2.00 |
2 |
| Lab |
Contact |
Lab to support content delivered. |
Every Week |
2.00 |
2 |
| Independent & Directed Learning (Non-contact) |
Non Contact |
Independent student learning. |
Every Week |
3.00 |
3 |
| Total Hours |
7.00 |
| Total Weekly Learner Workload |
7.00 |
| Total Weekly Contact Hours |
4.00 |
| Workload: Part Time |
| Workload Type |
Contact Type |
Workload Description |
Frequency |
Average Weekly Learner Workload |
Hours |
| Lecture |
Contact |
Lecture delivering theory underpinning learning outcomes. |
Every Week |
2.00 |
2 |
| Lab |
Contact |
Lab to support content delivered. |
Every Week |
2.00 |
2 |
| Independent & Directed Learning (Non-contact) |
Non Contact |
Independent student learning. |
Every Week |
3.00 |
3 |
| Total Hours |
7.00 |
| Total Weekly Learner Workload |
7.00 |
| Total Weekly Contact Hours |
4.00 |
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Module Resources
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| Recommended Book Resources |
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Pete Warden,Daniel Situnayake. (2020), Tiny ML: Machine Learning with Tensorflow Lite on Arduino and Ultra-Low-Power Microcontrollers, O'Reilly Media, p.0, [ISBN: 9781492052043].
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Wen-mei W. Hwu,David B. Kirk,Izzat El Hajj. (2022), Programming Massively Parallel Processors, 4th edition. Morgan Kaufmann, p.608, [ISBN: 9780323912310].
| | Recommended Article/Paper Resources |
|---|
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Jouppi, Norman P., et al.. (2017), In-datacenter performance analysis of a
tensor processing unit., Proceedings of the 44th annual
international symposium on computer
architecture..
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Wang, Xiaofei, et al.. (2020), Convergence of edge computing and deep
learning: A comprehensive survey, IEEE Communications Surveys &
Tutorials.
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Sze, Vivienne, et al.. (2017), Efficient processing of deep neural
networks: A tutorial and survey., Proceedings of the IEEE.
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Genc, Hasan, et al.. (2021), Gemmini: Enabling systematic
deep-learning architecture evaluation
via full-stack integration, 58th ACM/IEEE Design Automation
Conference (DAC).
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Vasilache, Nicolas, et al.. (2022), Composable and Modular Code Generation
in MLIR: A Structured and Retargetable
Approach to Tensor Compiler Construction, arXiv:2202.03293.
| | Other Resources |
|---|
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Website, Deploy machine learning models on mobile
and edge devices,
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