Module Details

Module Code: ELTR7010
Title: HDL Digital System Design
Long Title: HDL Digital System Design
NFQ Level: Intermediate
Valid From: Semester 1 - 2023/24 ( September 2023 )
Duration: 1 Semester
Credits: 5
Field of Study: 5230 - Electronic Engineering
Module Delivered in: 2 programme(s)
Module Description: This module will introduce students to techniques for the design and implementation of digital circuits using a Hardware Description Language (HDL). It will include concepts such as programmable logic , programmable logic systems, and digital system development software.
 
Learning Outcomes
On successful completion of this module the learner will be able to:
# Learning Outcome Description
LO1 Discuss the digital design process flow and describe the purpose and characteristics of each process step.
LO2 Describe the construction and characteristics of common reconfigurable logic circuit architectures.
LO3 Design a digital system using a common HDL (for example: Verilog, VHDL) and using a development system that can be interfaced to programmable logic ICs.
LO4 Simulate a digital system to verify its operation. Program a field-programmable gate array (FPGA) or complex programmable logic device (CPLD) from a recognised vendor to implement the simulated design.
LO5 Work as part of a team to design a complex digital system by partitioning a large design into a series of smaller sub-blocks which can be implemented by individuals or small groups and then merged together into a functional system.
Dependencies
Module Recommendations

This is prior learning (or a practical skill) that is strongly recommended before enrolment in this module. You may enrol in this module if you have not acquired the recommended learning but you will have considerable difficulty in passing (i.e. achieving the learning outcomes of) the module. While the prior learning is expressed as named MTU module(s) it also allows for learning (in another module or modules) which is equivalent to the learning specified in the named module(s).
Students will have a working knowledge of basic digital electronic concepts.
Incompatible Modules
These are modules which have learning outcomes that are too similar to the learning outcomes of this module. You may not earn additional credit for the same learning and therefore you may not enrol in this module if you have successfully completed any modules in the incompatible list.
No incompatible modules listed
Co-requisite Modules
No Co-requisite modules listed
Requirements

This is prior learning (or a practical skill) that is mandatory before enrolment in this module is allowed. You may not enrol on this module if you have not acquired the learning specified in this section.
No requirements listed
 
Indicative Content
Digital design techniques.
Introduction to digital design terminology, process flow, techniques, and concepts.
Programmable logic
Introduction to programmable logic architectures and systems.
Hardware Description Language (HDL)
HDL syntax, format, and application.
Digital design systems
Commercially common programmable logic systems from recognised vendors.
Module Content & Assessment
Assessment Breakdown%
Coursework100.00%

Assessments

Coursework
Assessment Type Practical/Skills Evaluation % of Total Mark 20
Timing Week 4 Learning Outcomes 3,4
Assessment Description
Design and simulate a digital circuit using a HDL
Assessment Type Practical/Skills Evaluation % of Total Mark 30
Timing Week 8 Learning Outcomes 3,4
Assessment Description
Design and simulate a complex digital circuit using a HDL
Assessment Type Practical/Skills Evaluation % of Total Mark 20
Timing Week 12 Learning Outcomes 3,4,5
Assessment Description
Work as part of a team to design, implement and simulate a complex digital system and report on how the design was partitioned.
Assessment Type Short Answer Questions % of Total Mark 30
Timing Week 13 Learning Outcomes 1,2,3
Assessment Description
Assessment of theoretical concepts
No End of Module Formal Examination
Reassessment Requirement
Coursework Only
This module is reassessed solely on the basis of re-submitted coursework. There is no repeat written examination.

The University reserves the right to alter the nature and timings of assessment

 

Module Workload

Workload: Full Time
Workload Type Contact Type Workload Description Frequency Average Weekly Learner Workload Hours
Lecture Contact Delivery of theory. Every Week 1.00 1
Lab Contact Practical application of theory. Every Week 3.00 3
Independent & Directed Learning (Non-contact) Non Contact Revision of class material. Preparation for lab work. Every Week 3.00 3
Total Hours 7.00
Total Weekly Learner Workload 7.00
Total Weekly Contact Hours 4.00
Workload: Part Time
Workload Type Contact Type Workload Description Frequency Average Weekly Learner Workload Hours
Lecture Contact Delivery of theory. Every Week 1.00 1
Lab Contact Practical application of theory. Every Week 2.00 2
Independent & Directed Learning (Non-contact) Non Contact Revision of class material. Preparation for mini project. Every Week 4.00 4
Total Hours 7.00
Total Weekly Learner Workload 7.00
Total Weekly Contact Hours 3.00
 
Module Resources
Supplementary Book Resources
  • Floyd. (2015), Digital Fundamentals, 11th Edition. [ISBN: 9780132737968].
This module does not have any article/paper resources
Other Resources
 
Module Delivered in
Programme Code Programme Semester Delivery
CR_EELES_8 Bachelor of Engineering (Honours) in Electronic Engineering 5 Mandatory
CR_EELXE_7 Bachelor of Engineering in Electronic Engineering 5 Mandatory